1. Field of the Invention
The present invention relates to a digital serial FIFO semiconductor memory.
2. Description of the Prior Art
A similar arrangement of transfer transistors is described in the German Offenlegungsschrift DE-A No. 24, 30 349, as part of a memory designed in accordance with the charge-transfer principle, and more particularly in accordance with the bucketbrigade principle, with the signal branches therein being referred to as transversal chains. The inputs of the signal branches and the outputs thereof are respectively connected to the tapping points of two further series of transfer transistors, which, in the aforementioned German Offenlegungsschrift are referred to as longitudinal chains. These are each independently clocked by separate clock signals as is characteristic for operation based upon the charge-transfer principle. The arrangement as described hereinbefore is suitable in particular for storing and, consequently, also for delaying analog signals or in a limiting case purely digital signals.
If digital signals are to be stored and, consequently, delayed in the sense of the first-in-first-out (FIFO) principle, it appears that the arrangement as described hereinbefore is too expensive with regard to the amount of semiconductor surface required for realizing the intended integrated circut, especially since each transfer transistor, in the arrangement as described hereinbefore, must be accompanied by a capacitor which likewise requires a certain surface area.
Therefore, it is the object of the invention that by utilizing parallel signal branches in the arrangement as described hereinbefore, a more space-saving arrangement can be provided which is suitable for use as a serial FIFO memory for digital signals.
Actually, FIFO memories can be realized with the aid of the well known dynamic random access memories (DRAMs). These, however, require suitable addressing. Moreover, up to a memory size of about 5 kilobits, the required semiconductor surface area, owing to the considerable proportion of so-called overheads, is so large that suitable loopholes have to be looked for. Overheads include all those partial circuits which are required in addition to the actual memory cells and are necessary for ensuring the safe operation thereof, such as the so-called dummy cells, the addressing and precharging stages for the bit and word lines, the write and read amplifier, the input and output buffer circuits, and etc.
Shift registers have also already been used in connection with FIFO memories, because they do not have the aforementioned disadvantage of overheads. The clock signal of the shift register, however, is required to have a frequency which is equal to that of the data rate of the input signals. This leads to rather considerable power losses in the shift register in the case of high clock frequencies.
In distinction to the foregoing, the power or dissipation loss occurring in the invention, owing to the clock signal frequency being reduced by the factor of n in the parallel signal branches, is reduced to about one n-th of the loss occurring in a usual type of shift register, with n indicating the number of parallel signal branches and, at the same time, the number of clock signals required for the total arrangement. Furthermore, for a conventional shift-register cell which, even in dynamic MOS circuits, consists of at least six transistors, there corresponds only one transfer transistor in the invention with its associated level regenerator, with this, for example, merely requiring three transistors.
The invention will now be explained in greater detail with reference to the accompanying drawings.